With the reduced size of a wiring structure and the increased number of layers in the wiring structure, much effort has recently been made to further integrate a semiconductor integrated circuit. As a method of forming a dense wiring pattern or a multilayer wiring structure, a damascene process is commonly used which forms wiring by using Cu as a wiring material and flattening the wiring material by means of CMP (Chemical Mechanical Polishing). On the other hand, the denser wiring pattern has disadvantageously increased a parasitic capacitance generated between wires. The increased parasitic capacitance reduces a speed at which signals are transmitted through the wiring. Thus, for the semiconductor integrated circuit which requires high-speed operations, it is important to reduce the parasitic capacitance between the wires.
For a method of reducing the parasitic capacitance between the wires, the use of a material with a low dielectric constant for an inter-wire insulating film and an interlayer insulating film has been considered. A silicon oxide (SiO2) film (dielectric constant: 3.9 to 4.2) has often been used as the inter-wire insulating film. In some semiconductor integrated circuits, an SiO2 film containing fluorine (F) (dielectric constant: 3.5 to 3.8) is used as an inter-wire insulating film that enables a reduction in dielectric constant as compared to the conventional SiO2 film. Moreover, to further reduce the electric parasitic capacitance between the wires, a proposal has been made of a semiconductor device using, as the inter-wire insulating film, a low-dielectric-constant film made up of a carbon-containing silicon oxide (SiOC) film with a dielectric constant of 3 or less.
A method of manufacturing the conventional semiconductor device will be described below with reference to FIGS. 6, 7A, 7B, 7C, 7D, 7E, 7F, 8A, 8B, 8C, and 8D.
FIG. 6 is a sectional view showing the wiring structure of the conventional semiconductor device. FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 8A, 8B, 8C, and 8D are sectional views showing the process of the method of manufacturing the conventional semiconductor device.
FIG. 6 shows the cross section of the wiring structure of the semiconductor device using the SiOC film as the inter-wire insulating film. In FIG. 6, a first insulating film 1 made up of an SiOC film is formed on a substrate (not shown) made up of silicon. A first metal wire 4 is formed in the first insulating film 1 and composed of a barrier metal 2 made up of tantalum nitride (TaN) and a conductive film 3 made up of copper (Cu). A second insulating film 5 is formed on the first insulating film 1 so as to cover the first metal wire 4; the second insulating film 5 is made up of silicon oxide containing carbon and nitrogen (SiCON) and functions as a metal diffusion preventing film. A third insulating film 6 made up of SiOC with a low dielectric constant is formed on the second insulating film 5. Here, a second metal wire 13 is formed in the third insulating film 6 and composed of a barrier metal 11 made up of TaN and a conductive film 12 made up of Cu. Furthermore, a metal via 14 is formed through the second insulating film 5 and the third insulating film 6 to connect the first metal wire 4 and the second metal wire 13 together. Finally, a fourth insulating film 15 is formed on the third insulating film 6. A pad electrode 16 made up of Al is formed in an opening in the fourth insulating film 15.
FIGS. 7A, 7B, 7C, 7D, 7E, 7F, 8A, 8B, 8C, and 8D show the sectional states of the respective steps of the method of manufacturing the semiconductor device shown in FIG. 6.
First, as shown in FIG. 7A, a wiring groove pattern is formed, by photolithography, on the first insulating film 1 formed on the substrate (not shown) and made up of SiOC. Subsequently, the first insulating film 1 is selectively etched by dry etching. Resist is then removed by ashing and cleaning to form a wiring groove. The barrier metal 2 made up of TaN and the conductive film 3 made up of Cu, are deposited so as to bury the wiring groove. Excess Cu is then removed by chemical mechanical polishing (CMP) to form the first metal wire 4.
Then, as shown in FIG. 7B, the second insulating film 5 made up of SiCON is deposited on the first insulating film 1 so as to cover the first metal wire 4. The third insulating film 6 is deposited, which is made up of SiOC and exhibits a low dielectric constant.
Then, as shown in FIG. 7C, a resist 7 is coated on the third insulating film 6, and a via pattern is formed in the resist 7 by photolithography. The insulating film 6 is subsequently etched by dry etching. The excess part of the resist is removed by ashing and cleaning to form a via hole 8 (FIG. 7D).
Then, as shown in FIG. 7E, a resist 9 is coated on the third insulating film 6, and a wiring pattern is formed in the resist 9 by photolithography. A wiring groove 10 used to form a second wire is formed in the third insulating film 6 by dry etching. The excess part of the resist 9 is then removed by ashing and cleaning (FIG. 7F).
Subsequently, the second insulating film 5 exposed at the bottom of the via hole 8 is etched away to complete the formation of the wire and via pattern in the second and third insulating films 5 and 6 (FIG. 8A).
Subsequently, as shown in FIG. 8B, the barrier metal 11 made up of TaN and the conductive film 12 made up of Cu are deposited so as to bury the wiring groove 10 and the via hole 8. The excess parts of Cu and TaN are then removed by chemical mechanical polishing (CMP) to form the second metal wire 13 and the via 14 as shown in FIG. 8C.
Finally, the fourth insulating film 15 made up of SiN is formed as a passivation film. The fourth insulating film 15 is partly formed into an opening by photolithography and etching. The Al pad electrode 16 is formed in the opening to complete a semiconductor device (FIG. 8D).
In general, a low-dielectric-constant film is likely to be damaged during the wiring process such as etching and ashing, resulting in an increase in dielectric constant. This makes it difficult to reduce the parasitic capacitance. Disadvantageously, such damage may be particularly affected by a process of patterning the wire using a resist mask. In the damascene process using the resist mask as described above, the low-dielectric-constant film in side walls of the wiring groove may be damaged by the ashing and cleaning process carried out after etching during the wire and via patterning steps using the resist mask. This increases the dielectric constant of the low-dielectric-constant insulating film and thus the effective dielectric constant of the wiring structure.
Thus, a proposal has been made of a wiring patterning process using a hard mask in order to eliminate or reduce the adverse effect of the damage during the process as described above.
As an example of a solution, description will be given of a damascene process of performing the conventional wire patterning using an insulating film hard mask. This method first uses the resist mask to form the wiring pattern on the insulating film hard mask, then ashes away the resist mask before forming the wiring groove pattern in the interlayer insulating film by etching, and then forms the wiring groove pattern in the interlayer insulating film by etching. According to this method, the resist mask is ashed away with the interlayer insulating film unexposed in the wiring groove. This enables a reduction in damage to the low-dielectric-constant insulating film in the side walls in the wiring groove due to ashing, which has been a problem with the process using the resist mask. The damascene process is thus characterized by using the interlayer insulating film with the low dielectric constant to provide a semiconductor device having the wiring structure with low effective dielectric constant.